1. Field of the Invention
This invention relates to semiconductor processing and more particularly to a semiconductor gate conductor which minimizes oxygen recombination at polysilicon/gate oxide and also at gate oxide/silicon substrate interface regions.
2. Background of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing a undoped polycrystalline material or "polysilicon" material over a relatively thin gate oxide, and implanting the polysilicon and adjacent source/drain regions with an impurity dopant material. Alternatively, the polysilicon can be diffusion doped prior to gate definition and source/drain implants. As defined herein, "gate conductor" refers to polysilicon material which has received an impurity implant and subsequent anneal necessary to activate the polysilicon to a conductive state. After polysilicon has received a dopant such as arsenic or boron, it becomes a gate conductor capable of providing a conduit for minority carrier movement.
It is well known that polysilicon material, which receives p+ dopants necessary to form PMOS devices, is more sensitive than the counterpart polysilicon used for NMOS devices. In CMOS manufacture embodying both PMOS and NMOS devices, it is important that the polysilicon overlying PMOS devices be carefully controlled during the anneal process. P+ dopants such as boron (B) can penetrate through the polysilicon, through the underlying gate oxide, and into the underlying silicon substrate or channel region. P+ dopants such as BF.sub.2 can dissiminate into B and fluorine (F), wherein B diffuses into the underlying silicon, but F diffuses only to the polysilicon/oxide and oxide/silicon interfaces. B dopants within the channel region can shift the threshold voltage (Vth) or the flat band voltage (Vfb) of the resulting PMOS device. In order to prevent B penetration (of B or BF.sub.2 dopant) into the underlying channel region, many manufactures maintain the hydrogen concentration in the annealing furnaces as low as possible. See, e.g., Sung, et al., "A Comprehensive Study on p+ Polysilicon-Gate MOSFET's Instability With Fluorine Incorporation", IEEE Trans. on Electron Devices, Vol. 37, No. 11, (November, 1990).
Doping the PMOS device polysilicon with B or BF.sub.2 implant material allows the resulting device to operate as a surface channel device rather than a buried channel device. The advantages of surface channel operation are: relieving short channel effects, and superior turn-off and turn-on characteristics. PMOS devices are typically fabricated in CMOS technology by implanting either B or BF.sub.2 into the polysilicon overlying the devices, followed by anneal. Due to BF.sub.2 having a larger atomic mass than B, BF.sub.2 is preferred material for achieving shallow source/drain junctions. Given the same electron-volt implant energy expended by the implant device, the larger atomic mass of BF.sub.2 will be driven to a lesser depth into the polysilicon and surrounding source/drain regions than B. The work function difference between a p+ gate and the underlying n-well is such that a surface channel PMOS device is realized.
Although BF.sub.2 is a mainstay in shallow junction/shallow channel PMOS fabrication for reasons stated hereinabove, fluorine (F) associated with BF.sub.2 can present numerous problems. Recent studies have indicated that F is highly mobile at the grain boundary sites of the polysilicon as well as within the underlying gate oxide. Enhanced diffusion along grain boundaries and interstitialcy movement within the underlying gate oxide allows F atoms to quickly travel to, and bond to, dangling or weakened bonds at the juncture between the oxide and the overlying polysilicon as well as at the juncture between the oxide and underlying silicon substrate. See, e.g., Wright, et al., "The Effect of Fluorine in Silicon Dioxide Gate Dielectrics", IEEE Trans. on Electron Devices, Vol 36, No. 5 (May, 1989). After the junctures or interface regions have been saturated with F, additional incorporation of F occurs primarily in the bulk of the oxide. As proposed by the article to Wright, et al., mobile F atoms appear to break the silicon-oxygen bonds and displace oxygen at the bond sites. The free oxygen (O) diffuses to the interface regions and oxidizes additional silicon therein. Oxide thickening is therefore a natural result of this phenomenon.
Referring now to FIG. 1, a cross-sectional view of a semiconductor substrate 10 is shown embodying a patterned PMOS device 14. Device 14 is placed between field oxides 16 and is configured to receive BF.sub.2 dopant ions. In particular, BF.sub.2 dopant ions are deposited within polysilicon material 18 and within adjacent source/drain regions 20 according to the well known self-aligned process. Spacers 22 can be employed to provide lightly doped drain regions, also well known to the skilled artisan.
As indicated by arrows 24, F associated with BF.sub.2 ions readily migrate or diffuse toward gate oxide material 26 from their initial deposit location within polysilicon 18. Weak silicon-oxygen bonds, at the interface regions between polysilicon 18 and oxide 26 as well as at the interface regions between oxide 26 and substrate 10, accept the mobile F atoms at the weakened bond sites.
Referring now to FIG. 2, a cross-sectional view of substrate 10, field oxide 16 and polysilicon 18 is shown. Furthermore, a thickened or enhanced gate oxide 26 is shown resulting from mobile F atoms dislodging oxygen at the silicon-oxygen bond sites, and the dislodged oxygen recombining at the interface regions. Recombination of oxygen with adjacent silicon at the interface regions causes growth or thickening of gate oxide 26 and the deleterious effects associated therewith.
Referring now to FIG. 3, a graph of concentration versus depth of F and O atoms within polysilicon 18, gate oxide 26 and substrate 10 is shown. Specifically, F atoms are illustrated as being highly mobile throughout polysilicon from their introduction point near the surface of the polysilicon through grain boundary locations and to underlying gate oxide 26. Interstitialcy movement of F atoms allow the atoms to initially concentrate at the interface regions thereby drawing free oxygen atoms from bonds at those regions which recombine to form thickened oxide. High level concentration of F atoms must thereby be controlled and minimized in the gate oxide area and, preferably, F should be reduced much lower than O concentration in the gate oxide so as to prevent recombination and dislodgment.
The displacement of O to the interface sites increases (i.e., thickens) gate oxide, leading to higher Vth, skewed Vfb, and slower gate operation. The displaced oxygen atom and resulting dangling bond on the silicon atom within the channel region underlying the oxide can act as a hole trap which would further deteriorate PMOS switching operation.
A proposed solution to alleviating the mobility of F and the problems associated therewith is to co-dope the BF.sub.2 implanted polysilicon with POCl.sub.3. Phosphorous within the POCl.sub.3 can act as a physical barrier by blocking available F diffusion sites at the interface regions. A result being a gate oxide region which does not thicken when F is introduced into the overlying polysilicon. See, e.g., Hsieh, et al., "Characteristics of MOS Capacitors of BF.sub.2 or B Implanted Polysilicon Gate With and Without POCl.sub.3 Co-doped", IEEE Electron Device Letters, Vol 14, No. 5 (May, 1993).
While POCl.sub.3 appears to have encouraging results, the method for introducing POCl.sub.3 is somewhat impractical under current CMOS manufacturing constraints. The proposed POCl.sub.3 material is primarily diffused only within PMOS regions. In order for POCl.sub.3 to be used with current CMOS processes, a masking step and blocking photoresist is required to prevent the POCl.sub.3 from entering the NMOS active regions. Since POCl.sub.3 is normally introduced by thermal diffusion, it is impractical for the blocking photoresist to be introduced into a high temperature diffusion furnace in order to selectively diffuse only the PMOS regions. Accordingly, studies into POCl.sub.3 barrier materials are generally limited to circuits which employ only PMOS devices. CMOS devices having the advantages of a F barrier cannot, as a practical matter, be formed using current POCl.sub.3 techniques.
It would be advantageous to provide a F barrier material which can be used to manufacture a CMOS device. The barrier material chosen must be capable of presenting a physical barrier at the polysilicon/gate oxide interface in order to minimize intertitialcy diffusion therein. The barrier material must also be capable of "stuffing" the grain boundaries in the polysilicon in order to decrease the rate of fluorine diffusion along the polysilicon grain boundaries. The barrier material must further be available in conventional processing devices and, once deposited, must not significantly trap mobility carriers within the polysilicon during gate operation.